1. Field of the Invention
The present invention relates to a method for manufacturing a field effect transistor and a transistor structure manufactured by the method. More particularly, the present invention relates to a method for manufacturing a field effect transistor comprising a channel consisting of silicon fins and a silicon body having an orientation different from the silicon fins, as well as a field effect transistor manufactured by the method.
2. Background of the Related Art
Currently, in an attempt to reduce the price of semiconductor devices and to improve the device performance, the size of semiconductor devices has continued to decrease according to the Moore's law, thus enabling the high integration of semiconductor IC chips.
However, as the channel length of semiconductor devices decreases to less than 100 nm, the potential of a channel in the prior field effect transistors is controlled not only by a gate but also by a drain region so that a phenomenon where great leakage current flows between the source and drain regions will occur even when devices are in an off-state.
To reduce this short-channel effect, ultra-thin body (UTB) transistor structures using, as a channel, a body consisting of the thin silicon thin film of an SOI (Silicon-on-insulator) wafer, and transistor structures using two or more gates, have been proposed. In the case of using the thin film channel, the effects of depletion charge and capacitance are reduced so that the short-channel effect can be effectively reduced without additional channel doping. This can reduce the problem of a reduction in mobility, caused by impurity scattering.
The double-gate structure is a silicon thin-film field-effect transistor manufactured by the prior SOI (silicon-on-insulator) complementary metal oxide semiconductor (CMOS) processing. In this structure, a channel is formed by locating gates on both sides of a silicon channel formed vertically to a substrate such that the ability of gate voltage to control the channel potential is enhanced to reduce leakage current.
After this, fin field effect transistor structures having reduced deviation in device characteristics between wafers and effective insulation between devices, and manufacturing methods thereof, and body-tied omega FinFET structures using a bulk substrate instead of an SOI substrate to solve the heat transfer problem of the fin field effect transistors, and manufacturing methods thereof, have been developed.
As a substitute for a two-dimensional structure for controlling the potential of a silicon channel using one gate electrode above the channel, a three-dimensional double-gate or multiple-gate transistor structure has been proposed in which gates are located above and below or both sides of a channel so as to maximize the ability to control the channel potential by gate voltage, and a thin silicon fin is used.
However, in the case of this three-dimensional vertical gate using a fin shape channel, the channel is formed in a sidewall having a crystal orientation of (110), unlike the case of a horizontal transistor where a channel is formed in a silicon body having a crystal orientation of (100). The mobility of electrons shows the highest value on the (100) plane and is lower on the order of (111) and (110) planes, and the mobility of holes shows the highest value on the (110) planes and is lower on the order of (111) and (100) planes.
As a result, an N-type fin field effect transistor having a channel formed in the (110) plane has a lower mobility and current value than a case where a channel is formed in the (100) plane. Also, the fin field effect transistor has a problem in that it is complicated to correct the channel width in the layout of devices.
In an attempt to solve this problem, a field effect transistor having a silicon fin and body was proposed which is manufactured by a similar process to a manufacturing process of the prior SOI transistor in a simple manner.
Hereinafter, a method for forming a silicon thin-film field-effect transistor according to the prior art and problems in the method will be described with reference to the accompanying drawings.
FIG. 1 is a process perspective view sequentially showing a method for manufacturing a fin field-effect transistor having gates formed on both sides of a fin, according to the prior art.
As shown in FIG. 1, on an SOI substrate 101 comprising a silicon substrate, a buried oxide film 102 and a silicon thin film 103a, a hard mask 104a is formed (10A).
Then, lithography is used to form a silicon channel pattern
Then, oxidation and etching are carried out to reduce the width of the above-formed fin (100C).
After growing or depositing a dielectric film for a gate 107 and the material of the gate 107, the region of the gate is patterned and implanted with ions to form a source/drain extension region (100E).
After forming spacers 108 on both sides of the gate 107, a source/drain region is formed by ion implantation (100E).
Using a self-aligned silicide process, electrodes 109 are formed, thus manufacturing a fin field-effect transistor (100F).
The device manufactured by this method has a shortcoming in that it requires a large area because the channel width of the device must be increased to increase the current value of the device. Another problem is that it is complicated to correct the device channel width in the device layout.
FIG. 2 is a process cross-sectional view showing a prior art method for manufacturing fin field-effect transistors, in which a bulk substrate is used to reduce the variation in device characteristics between wafers and to effectively achieve the insulation between the devices.
As shown in FIG. 2, on a bulk wafer 203a, a hard mask blocking layer 202a and a hard mask cap layer 201a are sequentially deposited (200A).
After the deposition, the hard mask blocking layer 202 and the hard mask cap layer 201 are patterned using optical lithography to form fin patterns consisting of a hard mask blocking layer 202b and a hard mask cap layer 201b (200B).
Using the patterned hard mask cap layer 201b and a fin height control layer, the bulk silicon substrate 203c is anisotropically etched to the desired depth to control the height of the fins (200C).
To control the growth rate of the substrate between the silicon channel and the fin during oxidation, the silicon channel is covered with a hard mask blocking layer and implanted with ions to form a damage layer 204 between the fins (200D).
By oxidation, an oxide film 205 with a different thickness is formed, and by etching, the oxide film grown on the side of the silicon channel is removed to form a silicon channel 206 (200E).
A gate dielectric film and a gate material are grown or deposited, thus manufacturing fin field-effect transistors on the bulk substrate (200F).
This structure has a problem in that it is difficult to control the exact height of the silicon channel, compared to the case of using the SOI substrate, because the height control layer having damages caused by the implantation of heavy ions is used to control the height of the fins. Also, it has a problem in that it requires a large area because the channel width of the devices must be increased to increase the current value of the devices. Still another problem is that it is complicated to correct the channel width in the layout of the devices.
FIG. 3 is a process cross-sectional view showing a prior art method for manufacturing an omega fin field-effect transistor, in which a bulk substrate is used to solve the heat transfer problem of the fin field-effect transistor.
As shown in FIG. 3, a silicon channel is formed in a silicon substrate using a trench process, and oxidation and etching are used to control the width of a fin where a channel and a source/drain region are to be formed (300A).
An oxide film is grown and a nitride film is deposited (300B).
Chemical vapor deposition is used to deposit an oxide film (300C).
Chemical-mechanical polishing (CMP) is performed using the nitride film as an etch stop layer (300D).
The nitride film is wet-etched and then implanted with ions so as to be able to control critical voltage (300E).
A gate dielectric film and a gate material are grown or deposited, thus manufacturing an omega fin field-effect transistor on the bulk substrate (300F).
This structure has a problem in that it is difficult to control the exact height of the silicon channel, compared to the case of using the SOI substrate, because the trench process is used to control the height of the fin.
Also, it has a problem in that it requires a large area because the channel width of the device must be increased to increase the current value of the device. Still another problem is that it is complicated to correct the channel width in the layout of the device.